Objective

To design a translator buffer between ECL and CMOS logic family that optimize the figure of merit (FOM) when driving the data bus at high frequency and maintain at the same time the given logic levels of at least .5V (low) and 3V (high) at Vout.

 

Procedure

We first considered a CMOS to be our buffer because if it works, not only our design will be simple but most important the FOM would be very small since the CMOS has small power dissipation, area and delay.  Unfortunately, the CMOS circuit did not work because it could not generate a large enough logic swing for our purpose.

Then, we briefly considered the option of having a buffer using a pull up resistor.  However, this option was rejected because of the large size and power dissipation of the resistor.

Our third choice was to use ECL_CMOS interfacing shown in the figure 7.57 of Gopalan.  We began our analysis in Pspice by running this ECL_CMOS interface alone, and varying the values of (W/L) of the PMOS AND NMOS until we obtained the required logic swings at the output of the CMOS load.  At this point, we thought we had found our ideal buffer, but as we continued to analyze the circuit, we saw that our ECL_CMOS circuit required an inverted signal as one of its inputs.  We used the guess and check method to find it. To make our buffer work, we needed to add a CMOS inverter with two negative sources as part of our buffer to invert the signal from the ECL driver.  The drawback of adding an extra inverter was that it added an extra step that increased propagation delay notably.

Next, we attempted to find the best aspect ratio that would maintain our logic levels. This step was fundamental to ensure the proper functionality of our buffer. We used the guess and check method to find it.  Pspice seemed to be the most efficient tool and the following is a table listing some samples of our results.

Buffer
Num. of Trials PMOS1 PMOS2 NMOS1 NMOS2 VOH (V) VOL (V) DELAY (ns)
1 1/1 1/1 20/1 20/1 2.64 0.84  
2 1/1 1/1 0.31/1 2.2/1 2.12 1.695 72.5
3 1/1 1/1 10/1 20/1 0.75 0.475  
4 1/1 1/1 10/1 15/1 1.2 1.68  
5 1/1 1/1 10/1 10/1 2.825 1.3  
6 1/1 1/1 10/1 5/1 4.05 3.61  
7 1/1 1/1 0.25/1 2.1/1 3.5 0.4 150

As the table illustrates, the aspect ratio that made changes to our logic levels were the ones for the NMOS.  Therefore, we kept the PMOS aspect ratio constant. From this data, we saw that there was a large propagation delay in the circuit.  This was a consequence of using small aspect ratios values for our buffer.  This large propagation delay made our FOM large. Note that the delay power was not calculated for the entries that gave wrong logic levels.

Pspice Output

 

Calculations

Attached to this page are sample calculations that show how power dissipation, area and propagation delay were calculated in order to compute the best FOM of our circuit.  The hand calculations for propagation delay and power dissipation are not close with Pspice results.  We computed and revised our calculation to find algebraic and/or conceptual errors, but we could not find what was our error.  The only explanation we came up with was that circuit is not totally linear, so that superposition, which was the method used, did not give accurate results as Pspice.

From the attached calculations, it was observed that the CMOS load contribution to the FOM was very small.  The current for both low and high output was in the microamperes making power dissipation small.  Similarly, the area and propagation delay was small.

Contrary to the CMOS load, the ECL driver has a larger power dissipation and area due to the emitter resistor.

Unfortunately, our translator buffer provided the most contribution to the propagation delay of the circuit.  This was due to the extra step needed to invert the incoming ECL signal. We compensated for this delay by making our translator buffer’s area contribution to the FOM negligible compared with the total area of the circuit, and having small power dissipation.

Here is a table summarizing factors used to calculated FOM

Frequency Total Propagation Delay Total Average Power (mW) Total Area (Buffer Only) (um2) Maximum Frequency Calculated FOM
1 kHz 72.5 15.2 24.5 33.3 Mhz 27,052

Calculation sample

 

Conclusion

This project gave us the opportunity to exercise our knowledge about interfacing by making us use our MOHAT analysis skills to design the buffer that fulfilled all the given specifications. Although, our buffer has a large propagation delay, it still satisfied the design specifications.  Our buffer has a 3.7V (high) and .4V(low) logic levels at Vout, which are better than the one required.  It also operated at to a high frequency of about 33 MHz without serious distortion. 27052 was the best FOM achieved